1. Field of the Invention
The present invention relates to an instruction control mechanism for processors capable of executing an instruction set efficiently with a simple configuration and, in particular, to a technique for realizing an instruction control mechanism for processors capable of executing an instruction set which can use abbreviated instructions for a smaller program size, and a multiplicity of instructions efficiently, with a simple configuration.
2. Description of the Related Art
The instruction set that can be executed is predetermined for a given processor. The instruction code constituting the instruction set includes an instruction field (operation code) and at least one operand. The instruction field is a portion representing the instruction to be processed, and the operand is a portion representing a register or a memory address. The operand may be a numerical value used for the processing. Such a numerical value is called an immediate value or a literal.
There are various types of instructions including an instruction with a single operand such as a jump instruction, an instruction having two operands to be added or otherwise calculated with the result thereof stored in one of the operands, an instruction having two operands from one of which a value is moved to the other, and an instruction having three operands with two of them added or otherwise calculated with the result thereof stored in the remaining operand. An instruction having three operands can be realized by combining instructions having two operands, and therefore some instruction sets have no instruction having three operands. The description that follows concerns an instruction set having three addressing modes using one, two or three operands, respectively. The instruction in addressing mode using only a register is called a register instruction, and the instruction in addressing mode using an immediate address is called an immediate instruction. The present invention handles an instruction set in which the register instruction has the same length as the immediate instruction.
With the trend toward higher speed and lower cost in recent years, various processes which have thus far been executed using dedicated circuits have come be executed with a single processor by switching the program. This has given rise to various problems, however, including an extremely increased program size, an increased number of memories, such as caches, built in a chip or external memories and an increased power consumption due to the fact that such memories are accessed more frequently. The widespread use of portable communication and other electronic equipments has caused the processor cost and the power consumption to represent a considerable proportion of the overall cost of the equipment. The problem is then how to reduce the whole program size of the processor. It is therefore desirable for an instruction set, if predetermined in length, to contain as many instruction codes as possible in it.
Another solution to this problem is to use abbreviated instructions. The use of abbreviated instructions can reduce the program size. A conventional processor is available with which abbreviated instructions can be used as well as basic-length instructions. In a conventional example method permitting the use of both basic-length instructions and abbreviated instructions, a bit indicating the instruction length is inserted in the instruction field beforehand to identify the instruction in a program as a basic-length instruction or as an abbreviated instruction. In this method, however, the use of one bit for this identification undesirably reduces the number of bits available for the other fields.
In view of this, according to another conventional method, the mode is switched in response to a mode switching instruction in a program by a mode switching means included in the processor. In abbreviated instruction mode, all the instruction codes are processed as abbreviated ones. In this method, however, the instructions not assigned for the abbreviated instruction set cannot of course be used. Since all the basic-length instructions cannot be basically assigned for abbreviation, it follows that some instructions included in the basic-length instruction set cannot be used as an abbreviated instruction. Such instructions cannot be used in abbreviated instruction mode, and if such instructions are to be used, it is necessary to convert them into basic-length instructions. This complicates the program and increases the size of the program.
The above-mentioned two methods use the same length of the instruction field for both the basic-length instructions and the abbreviated instructions. Nevertheless, many instructions can be held as abbreviated instructions by differentiating the structure of the instruction field between the basic-length instruction set and the abbreviated instruction set. If an instruction decoder is to be shared for that purpose in a processor capable of executing the two types of instruction sets by switching, however, a conversion circuit is required for converting an abbreviated instruction field into a basic-length instruction field. In the normal processing operation, the conversion circuit consumes a stage of pipelines or at least imposes a burden on the critical path of the decoder, resulting in the problem of an increased hardware size and a deteriorated performance due to an increased branch penalty.